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| pi2001 cool-oring tm series universal active oring controller ic description the pi2001 cool-oring tm solution is a universal high-speed active oring controller ic designed for use with n-channel mosfets in redundant power system architectures. the pi2001 cool-oring controller enables an extremely low power loss solution with fast dynamic response to fault conditions, critical for hi gh availability systems. the pi2001 controls single or parallel mosfets to address active oring applications protecting against power source failures. the pi2001 can be used in either high-side or low-side active oring applications and a master/slave feature allows the paralleling of ic/mosfet chipsets for high current active oring. the gate drive output turns the mosfet on in normal steady state operation, while achieving high- speed turn-off during input power source fault conditions, that cause re verse current flow, with auto-reset once the fault clears. the mosfet drain-to-source voltage is monitored to detect normal forward, excessive forward, light load and reverse current flow. the pi2001 provides an active low fault flag output to the system during excessive forward current, reverse current, light load, over- voltage, under-voltage and over-temperature fault conditions. there is an internal shunt regulator at the vc input for high voltage applications and the under-voltage and over-voltage thresholds are programmable via external resistor dividers. features ? fast dynamic response to power source failures, with 160ns reverse current turn-off delay time ? 4a gate discharge current ? accurate mosfet drain-to-source voltage sensing to indicate system level fault conditions ? programmable under & over-voltage detection ? over temperature fault detection ? adjustable reverse current blanking timer ? 100v for 100ms operation in low side applications ? master/slave i/o for paralleling (tdfn only) ? active low fault flag output applications ? n+1 redundant power systems ? servers & high end computing ? telecom systems ? low & high-side active oring ? high current active oring package information the pi2001 is offered in the following packages: ? 10 lead 3mm x 3mm tdfn package ? 8 lead soic package typical applications: figure 1a: pi2001 high side active oring figure 1b: pi2001 low side active oring picor corporation ? picorpower.com pi2001 rev 1.0 page 1 of 23
pin description pin number pin name 10 lead tdfn 8 lead soic description gnd 1 1 ground: this pin is ground for the gate driver and control circuitry. gate 2 2 gate drive output: this pin drives the gate of the external n-channel mosfet. under normal operating conditions, the gate pin pulls high to 9.5v (typ) with respect to the sp pin. the controller turns the ga te off during a reverse current fault that exceeds the reverse voltage threshold. vc 3 3 controller input supply: this pin is the supply pin for the control circuitry and gate driver. connect a 1 f capacitor between vc pin and the gnd pin. voltage on this pin is limited to 15.5v by an internal shunt regulator. for high voltage auxiliary supply applications connect a shunt resistor be tween vc and the auxiliary supply. sl 4 n/a slave input-output: this pin is used for paralleling multiple pi2001 solutions in high power applications. when the pi2001 is conf igured as the master, this pin functions as an output capable of driving up to 10 sl pins of slaved pi2001 devices. it serves as an input when the pi2001 is configured in slave mode. bk 5 4 blanking timer input-output: connect a resistor from bk to gnd to set the blanking time for the reverse comparator function. to configure the controller in slave mode, connect bk to vc. to configure the controlle r in master mode with the fastest turn-off response, connect bk directly to gnd. f t 6 5 fault state output: this open collector pin pulls low when a fault occurs. fault logic inputs are vc under-voltage, input under-vol tage, input over-voltage, forward over- current, light load, reverse current, and over-temperature. leave this pin open if unused. sp 7 6 positive sense input & clamp: connect sp pin to the source pin of the external n- channel mosfet. the polarity of the voltage difference between sp and sn provides an indication of current flow direction through the mosfet. sn 8 7 negative sense input & clamp: connect sn to the drain pin of the external n- channel mosfet. the polarity of the voltage difference between sp and sn provides an indication of current flow direction through the mosfet. uv 9 8 input under-voltage input: the uv pin is used to detect an input source under- voltage condition in ground referenced applications. when the uv pin voltage drops below the uv threshold, the f t pin pulls low indicating a fault condition. the input voltage uv threshold is programmable through an external resistor divider. connect uv to vc to disable this function. ov 10 n/a input over-voltage input: the ov pin is used to detect an input source over-voltage condition in ground referenced applications . when the ov pin voltage crosses the ov threshold, the f t pin pulls low indicating a fault condition. the input voltage ov threshold is programmable through an external resistor divider. connect ov to gnd to disable this function. package pin-outs 10 lead tdfn (3mm x 3mm) top view 8 lead soic (5mm x 6mm) top view picor corporation ? picorpower.com pi2001 rev 1.0 page 2 of 23 absolute maximum ratings vc -0.3v to 17.3v / 40ma sp, ov, sl -0.3v to 8.0v / 10ma uv, bk, ft -0.3v to 17.3v / 10ma gate -0.3v to 17.3v / 5a sn (continuous) -0.3v to 80v / 10ma sn (100ms pulse) 100v / 10ma gnd -0.3v / 5a peak storage temperature -65 o c to 150 o c operating junction temperature -40 o c to over temperature fault (t ft ) lead temperature (soldering, 20 sec) 250 o c esd rating 2kv hbm electrical specifications unless otherwise specified: -40 c < t j < 125 c, vc =12v, c vc = 1uf, c gate = 4nf, c sl = 10pf parameter symbol min typ max units conditions vc supply operating supply range (3) v vc-gnd 4.5 13.2 v no vc limiting resistors quiescent current i vc 3.7 4.2 ma normal operating condition, no faults vc clamp voltage v vc-clm 15 15.5 16 v i vc =10ma vc clamp shunt resistance r vc 7.5 delta i vc =10ma vc under-voltage rising threshold v vcuvr 4.3 4.5 v vc under-voltage falling threshold v vcuvf 4.0 4.15 v vc under-voltage hysteresis v vcuv-hs 150 mv fault under-voltage rising threshold v uvr 500 540 mv under-voltage falling threshold v uvf 440 475 mv under-voltage threshold hysteresis v uv-hs 25 mv under-voltage bias current i uv -1 1 a over-voltage rising threshold v ovr 500 540 mv over-voltage falling threshold v ovf 440 475 mv over-voltage threshold hysteresis v ov-hs 25 mv over-voltage bias current i ov -1 1 a fault output low voltage v ftl 0.2 0.5 v i ft =2ma, vc>3.5v fault output high leakage current i ft-lc 10 a v ft =14v fault delay time t ft-del 20 40 60 s includes output glitch filter picor corporation ? picorpower.com pi2001 rev 1.0 page 3 of 23 picor corporation ? picorpower.com pi2001 rev 1.0 page 4 of 23 electrical specifications unless otherwise specified: -40 c < t j < 125 c, vc =12v, c vc = 1uf, c gate = 4nf, c sl = 10pf parameter symbol min typ max units conditions fault (continued) over temperature fault (1) t ft 160 c over temperature fault hysteresis (1) t ft-hs -10 c differential amplifier and comparators common mode input voltage v cm -0.1 5.5 v sp to gnd & sn to gnd differential operating input voltage v sp-sn -50 125 mv sp-sn sp input bias current i sp -50 -37 a sp=sn=1.25v sn input bias current i sn 3.5 8 a sp=sn=1.25v sn voltage v sn 80 v i sn ? 7ma,sp=0v, i vc = 10ma reverse comparator off threshold v rvs-th -10 -6 -2 mv v cm = 3.3v reverse comparator hysteresis v rvs-hs 2 5 mv v cm = 3.3v reverse fault to gate turn-off delay time t rvs-ms 160 220 ns v sp-sn = 50mv step to 90% of v g max, v bk =0 (minimum blanking) reverse fault to gate turn-off delay time t rvs-sl 430 600 ns v sp-sn = 50mv step to 90% of v g max, v bk = v vc (maximum blanking) forward comparator on threshold v fwd-th 2 6 9 mv v cm = 3.3v forward comparator hysteresis v fwd-hs -5 -2 mv v cm = 3.3v forward over-current comparator threshold v oc-th 60 66 70 mv v cm = 3.3v forward over-current comparator hysteresis v oc-hs -8 -4 mv v cm = 3.3v gate driver gate source current i g-sc -1.0 -0.4 ma v g = 1v, normal operating conditions, no faults pull down peak current (1) i g-pd 1.5 4.0 a pull-down gate resistance (1) r g-pd 0.3 v g = 1.5v @ 25 c ac gate pull-down voltage (1) v g-pd 0.2 v dc gate pull-down voltage to sp (1) v g-pd 1.1 v i g =100ma, in reverse fault gate voltage @ vc uvlo v g-uvlo 0.7 1 v i g =10 a,1.5v forward voltage comparator: fwd the fwd comparator detects when a forward current condition exists and sp is 6mv(typical) positive with respect to sn. when sp-sn is less than 6mv, the fwd comparator will assert the fault flag to report a fault condition indicative of a light load or ?load not present? condition or possible shorted mosfet. forward over current comparator: foc the foc comparator indicates an excessive forward current condition when sp is 66mv(typical) higher than sn. when the gate output voltage is greater than 77% of the regulated gate voltage and sp-sn is higher than 66mv, the pi2001 will initiate a fault condition via the f t pin. slave: in high current applications multiple parallel mosfets may be needed for a single oring function. driving multiple mosfets with one controller will increase the loading on the gate pin and the gate connection parasitic thereby impacting the reverse turn-off response. the slave function synchroni zes multiple controllers so that one, or more, of the paralleled mosfets will have its own local driving source. in this configuration, one controller will be designated as the master and it will control the response of the slaved controllers. when the controller is configured in ?master mode?, by connecting the bk to ground, the sl will be an output having the same signal characteristics as the gate signal. in this configuration, the sl output is capable of driving up to ten controllers, configured in ?slave mode?, through their corresponding sl pins. logic high for the sl pin is limited to 5.5v (max). when the bk pin is tied to vc, the controller is configured in ?slave mode? and the sl pin becomes an input. the gate driver section and reverse current section are the only active circuits in the slave controller while the master performs the diagnostics and gate drive control. vc and internal voltage regulator: the pi2001 has a separate i nput (vc) that provides power to the control circuitry and the gate driver. an internal regulator clamps the vc voltage to 15.5v. picor corporation ? picorpower.com pi2001 rev 1.0 page 7 of 23 for high side applications, the vc input should be high enough above the bus voltage to properly enhance the external n-channel mosfet. in a low side drive application vc may be tied to the bus voltage through a resistor. the internal regulator circuit has a comparator to monitor vc voltage and initiates a fault condition when vc is lower than the vc under-voltage threshold. uv: the under-voltage (uv) input trip point can be programmed through an external resistor divider to monitor the input voltage. the uv comparator initiates a fault condition and pulls the f t pin low when uv falls below the under-voltage falling threshold. the gate pin does not respond to a uv fault. if the pi2001 is configured in a floating application, where the gnd pin is connected to the input voltage, the uv pin cannot detect the input voltage. in this case, the uv pin should be disabled by connecting it to the vc pin. ov : the over voltage (ov) input trip point can be programmed through an external resistor divider to monitor the input voltage. the ov comparator initiates a fault condition and pulls the ft pin low when ov rises above the over-voltage rising threshold. the gate pin does not respond to an ov fault. if the pi2001 is configured in a floating application, where the gnd pin is connected to the input voltage, the ov pin cannot detect the input voltage. in this case, the ov pin should be disabled by connecting it to the gnd pin. over-temperature detection: the internal over-temperature block monitors the junction temperature of the controller. the over- temperature threshold is set to 160 c with -10 c of hysteresis. when the controller temperature exceeds this threshold, th e over-temperature circuit initiates a fault condition and pulls the ft pin low. by maintaining proper thermal matching between the controller and the power mosfet, this function can be used to protect the oring device from thermal runaway conditions. the gate pin does not respond to an over-temperature fault. gate driver: the gate driver (gate) output is configured to drive an external n-channel mosfet. in the high state, the gate driver applies a 1ma current source to the mosfet gate and regulates the voltage to 9.5v typical (v g-clmp ) above the sp pin voltage (v sp ) when the vc input voltage is higher than v sp plus v g-clmp . otherwise the gate voltage (v g ) to v sp will be {v g-sp = vc - v sp ? 0.5v}. note that vc is the controller internal regulated voltage. when a reverse current faul t is initiated, the gate driver pulls the gate pin low and discharges the fet gate with 4apeak capability. when the input source voltage is applied and before the mosfet is fully enhanced, a voltage greater than the forward over curr ent (foc) threshold will be present across the mosfet. to avoid an erroneous foc detection, a vgs detector blanks the foc and fwd comparators from initiating a fault, until the gate pin reaches 77% of v g-clmp . if vc is too low to establish the gate clamp condition the reference for detection is 77% of {vc-v(sp) - 0.25v}. fault: the fault circuit output is an open collector with 40 s delay to prevent any false triggering. the f t pin will be pulled low when any of the following faults occur: x reverse current x forward over-current x forward low current x over-temperature x input under-voltage x input over-voltage x vc pin under-voltage the only fault condition that initiates gate turn-off of the mosfet (as well as a fault flag signal) is when the reverse current fault conditions are met. all other fault conditions issue only a fault flag signal via the f t pin, but do not affect the gate of the mosfet. the f t pin serves as an indicator that a fault condition may be present. this information can be reported to a host to signal that some system level maintenance may be required. picor corporation ? picorpower.com pi2001 rev 1.0 page 8 of 23 figure 3: pi2001 controller internal block diagram (10 lead tdfn package pin out shown) figure 4: comparator hysteresis, values are for reference on ly, please refer to the electrical specifications picor corporation ? picorpower.com pi2001 rev 1.0 page 9 of 23 figure 5: pi2001 state diagram (configured in master mode) picor corporation ? picorpower.com pi2001 rev 1.0 page 10 of 23 figure 6: timing diagram for two pi2001 controllers in an active oring application picor corporation ? picorpower.com pi2001 rev 1.0 page 11 of 23 typical characteristics: figure 7: controller bias current vs. temperature figure 8: vc uvlo threshold vs. temperature figure 9: reverse condition gate turn-off delay time vs. temperature. figure 10: reverse comparator threshold vs. temperature. v cm: common mode voltage . figure 11: gate to sp clamp voltage vs. temperature. figure 12: gate output source current vs. temperature picor corporation ? picorpower.com pi2001 rev 1.0 page 12 of 23 application information: the pi2001 is designed to replace oring diodes in high current redundant power architectures. replacing a traditional diode with a pi2001 controller ic and a low on-state resistance n-channel mosfet will result in significant pow er dissipation reduction as well as board space reducti on, efficiency improvement and additional protection features. this section describes in detail the procedure to follow when designing with the pi2001 active oring controller and n-channel mosfets. three different active oring design examples are presented. fault indication: f t output pin is an open collector and should be pulled up to the logic voltage or to the controller vc via a resistor (10k ? ) blanking timer: connect the blanking timer pin (bk) to gnd to program the device for the fastest reverse comparator response time of 160ns typical. to increase the blanking time, connect the bk pin to gnd via a resistor to avoid the fault response to short reverse current pulses. refer to figure 2 in the reverse comparator functional description for resistor values versus the reverse blanking time. auxiliary power supply (vaux): vaux is an independent pow er source required to supply power to the pi2001 vc input. the vaux voltage should be higher than vin (redundant power source output voltage) by the required gate-to-source voltage (vgs) to fully enhance the mosfet, plus 0.5v maximum gate to vc headroom (vhd vc-g ) vaux = vin + vgs + vhd vc-g where, vhd vc-g is defined as the 0.5v maximum drop from vc in the gate voltage high (v g ) specification in the gate driver section of t he electrical specification. for example, if the bus voltage is 3.3v and the mosfet requires 5.0v of vgs to fully enhance the mosfet, then vaux should be at least 3.3v + 5.0v + 0.5v = 8.8v. if vaux is higher than 15v then a bias resistor (rbias) is required, and should be connected between the pi2001 vc pin and vaux. the resistor is selected based on the input voltage range. minimize the resistor value for low vaux voltage levels to avoid a voltage drop that may reduce the vc voltage lower than required to drive the gate of the mosfet. select the value of rbias using the following equations: max min ic vc vaux rbias clamp rbias maximum power dissipation: r bias vc vaux pd clamp rbias 2 max ) ( rbias maximum power dissipation is at maximum input voltage and minimum clamp voltage (15v). where: min vaux : vaux minimum voltage max vaux : vaux maximum voltage clamp vc : controller clamp voltage, 15.5v max ic : controller maximum bias current (4.2ma) slave : for a high current application where one mosfet can not handle the total load current, multiple mosfets can be paralleled and driven by a single pi2001 controller. special care has to be taken when multiple mosfet gates are driven from one gate driver output. the gate driver output capability will be divided by the number of mosfet gates connected to it and will slow the mosf et response to a reverse fault. to avoid mosfet slow response the pi2001 can be configured in a master / slave configuration providing localized gate drive to each paralleled mosfet. the pi2001 slave feature allows the user to parallel multiple pi2001s and configure one unit as the master and the rest in slave mode. the slave ( sl ) pin of the master unit will act as an output driving the units configured in slave mode. the sl pins of the slaved units will act as inputs under the control of the master. in this configuration each mosfet will have its own localized gate driver which is synchronized by the master controller, thereby improving the response to a reverse current condition. one master controller is capable of driving up to 10 slave inputs. n-channel mosfet selection: there are several factors that affect the mosfet selection including cost, on-state resistance (rds(on)), current rating, power dissipation, thermal conductivity, drain-to-source breakdown voltage (bvdss), gate-to- source voltage rating (vgs), and gate threshold voltage (vgs (th) ). the first step is to select suitable mosfets based on the bvdss requirement for the application. the bvdss voltage rating should be higher than the applied vin voltage plus expected transient voltages. stray parasitic inductance in the circuit can also contribute to significant transient voltage conditions, particularly picor corporation ? picorpower.com pi2001 rev 1.0 page 13 of 23 during mosfet turn-off after a reverse current fault has been detected. in active oring applications when one of the input power sources is shorted, a large reverse current is sourced from the circuit output through the mosfet. depending on the output impedance of the system, the reverse current may reach over 60a in some conditions before the mosfet is turned off. such high current conditions will store energy even in a small parasitic element. for example, a 1nh parasitic inductance with 60a reverse current w ill store 1.8j (?li 2 ). when the mosfet is turned off, the stored energy will be released and will produc e high negative voltage ringing at the mosfet source. this event will create a high voltage difference across the drain and source of the mosfet. the mosfet current rating and maximum power dissipation are closely related. generally the lower the mosfet rds(on), the higher the current capability and the lower the resultant power dissipation. this leads to reduced thermal management overhead, but will ultimately be higher cost compared to higher rds(on) parts. it is important to understand the primary design goal objectives for the application in order to effectively trade off the performance of one mosfet versus another. power dissipation in active oring circuits is derived from the total source current and the on-state resistance of the selected mosfet . mosfet power dissipation: )( 2 onrdsis pd mosfet ?= where : is : source current rds(on) : mosfet on-state resistance note: in the calculation use rds(on) at maximum mosfet temperature because rds(on) is temperature dependent. refer to the normalized rds(on) curves in the mosfet manufacturers datasheet. some mosfet rds(on) values may increase by 50% at 125c compared to values at 25c. the junction temperature rise is a function of power dissipation and thermal resistance. )( 2 onrdsisrth pdrth trise ja mosfet ja mosfet ??=?= , where: ja rth : junction-to-ambient thermal resistance rds(on) and pi2001 sensing: the pi2001 senses the mosfet source-to-drain voltage drop via the sp and sn pins to determine the status of the current through the mosfet. when the mosfet is fully enhanced, its source-to-drain voltage is equal to the mosfet on-state resistance multiplied by the source current, v sd = rds(on)*is. the reverse current threshold is set for -6mv and when the differential voltage between the sp & sn pins is less than -6mv, i.e. sp-sn -6mv, the pi2001 detects a reverse current fault condition and pulls the mosfet gate pin low, thus turning off the mosfet and preventing further reverse current. the reverse current fault protection disconnects the power source fault condition from the redundant bus, and allows the system to keep running. the gate pin output voltage is clamped to 10.5v maximum with respect to the sp pin, which should be tied to the mosfet source pin, to support any mosfet with a vgs rating of 12v or greater. a vgs rating 12v is very common for industry standard n- channel mosfets. ov/uv resistor selection: the uv and ov comparator inputs are used to monitor the input voltage and will indicate a fault condition when this voltage is out of range. the uv and ov pins can be configured in two different ways, either with a divider on each pin, or with a three- resistor divider to the same node, enabling the elimination of one resistor. under-voltage is monitored by the uv pin input and over-voltage is monitored with the ov pin input. the fault pin ( f t ) will indicate a fault (active low) when the uv pin is below the threshold or when the ov pin is above the threshold. the uv and ov thresholds are 0.50v typ with 25mv hysteresis and their input current is less than 1a. it is important to consider the maximum current that will flow in the resistor divider and maximum error due to uv and ov input current. set the resistor current to 100a or higher to maintain 1% accuracy for uv and ov due to the bias current. the three-resistor voltage divider configuration for both uv and ov to monitor the same voltage node is shown in figure 13: ra th i ovv ra )( = figure 13: uv & ov three-resistor divider configuration. picor corporation ? picorpower.com pi2001 rev 1.0 page 14 of 23 ra th i ovv ra )( = set value based on system allowable current ra ra i ra th i ovv ra )( = ? ? ? ? ? ? ? ? ? = 1 )( )( uvv ovv rarb () ? ? ? ? ? ? ? ? ? += 1 )( th v uvv rbrarc where: )( th uvv : uv threshold voltage )( th ovv : ov threshold voltage v(uv) : uv voltage ra i : current. ra alternatively, a two-resistor voltage divider configuration can be used and is shown in (figure 14). figure 14: two-resistor divider configuration the uv resistor voltage divider can be obtained from the following equations: ruv th uv i uvv r )( 1 = set value based on system allowable current uv r 1 a i ruv 100 ? ? ? ? ? ? ? ? ? = 1 )( )( 12 th uv uv uvv uvv rr where: )( th uvv : uv threshold voltage ruv i : current uv r 1 ruv th uv i uvv r )( 1 = set value based on system allowable current ov r 1 a i ruv 100 ? ? ? ? ? ? ? ? ? = 1 )( )( 12 th ov ov ovv ovv rr picor corporation ? picorpower.com pi2001 rev 1.0 page 15 of 23 where: )( th ovv : ov threshold voltage rov i : current ov r 1 typical application example 1: requirement: redundant bus voltage = 3.3v load current = 15a (assume through each redundant path) maximum ambient temperature = 75c auxiliary voltage = 12v (11v to 13v) solution: 1. a single pi2001 with suitable external mosfet for each redundant 3.3v power source should be used, configured as shown in the circuit schematic in figure 15 2. select a suitable n-channel mosfet: most industry standard mosfets have a vgs rating of +/-12v or higher. select an n-channel mosfet with a low rds(on) which is capable of supporting the full load current with some margin, so a mosfet capable of at least 18a in steady state is reasonable. an exemplary mosfet having these characteristic is fds6162n7 from fairchild. from fds6162n7 datasheet: ? n-channel mosfet ? v ds = 20v ? i d = 23a continuous drain current ? v gs ( max )= 12v ? r ja = 40c/w ? r ds(on) =2.9m typical at i d =23a, v gs ? 4.5v, t j =25c reverse current threshold is: a m mv onrds reversevth reverseis 07.2 9.2 6 )( . . ?= ? = = power dissipation: rds(on) is 3.5m maximum at 25c & 4.5vgs and will increase as the temperature increases. add 25c to maximum ambient temperature to compensate for the temperature rise due to power dissipation. at 100c (75c + 25c) rds(on) will increase by 28%. = ? = m monrds 48.428.15.3)( maximum at 100c )( 2 onrdsisrthtrise ja ??= maximum junction temperature tris e tt a j + = max c ma w c ct j = ? ? ? ? ? ? ?? += 115 48.4)15( 40 75 2 max recalculate based on calculated junction temperature, 115c. at 115c rds(on) will increase by 32%. =?= m monrds 62.432.15.3)( c ma w c ct j = ? ? ? ? ? ? ?? += 5.116 62.4)15( 40 75 2 max 3. vaux: make sure vaux voltage is higher than vin (power source output) by the voltage required to fully enhance the mosfet. minimum required vaux = vin + vgs + 0.5v = 3.3v + 4.5v + 0.5v = 8.3v. since 8.3v is less than the 11v minimum aux supply voltage, there is sufficient voltage available to drive the gate of the mosfet. 4. sp and sn pins: connect the sp pin to the mosfet source pin and the sn pin to the mosfet drain pin. 5. bk pin: connect the bk pin to the gnd pin to achieve the minimum reverse current response time. 6. sl pin: not required, so leave floating. 7. f t pin : connect to the logic input and to the logic power supply via a 10k resistor. 8. program uv and ov to monitor input voltage: program uv at 3.0v and ov at 3.6v use the three-resistor divider configuration: ai ra 200 = == = k a mv i uvv ra ra th 5.2 200 500 )( or 2.49k 1% ? ? ? ? ? ? ? ? ? = 1 )( )( uvv ovv rarb = ? ? ? ? ? ? ?= 4981 0.3 6.3 49.2 v v k or 499 1% () ? ? ? ? ? ? ? ? ? += 1 )( )( th uvv uvv rbrarc () = ? ? ? ? ? ? ? += k mv v k 95.141 500 0.3 49949.2 or 15k 1% figure 15: pi2001 in high side active oring configuration picor corporation ? picorpower.com pi2001 rev 1.0 page 16 of 23 typical application example 2: requirement: redundant bus voltage = 12v (10%, 10.8v to 13.2v) load current = 10a (assume through each redundant path) maximum ambient temperature = 75c auxiliary voltage = 24v10% (21.6v to 26.4v) referenced to gnd solution: 1. a single pi2001 with suitable external mosfet for each redundant 12v power source should be used, configured in a high-side floating configuration as shown in the circuit schematic in figure 16. the controller is floated on vin by connecting the controller ground pin to the input voltage vin. 2. select a suitable n-channel mosfet: select an n-channel mosfet with a voltage rating higher than the 12v input plus any expected transient voltages, with a low rds(on) that is capable of supporting full load current with margin. for instance, a 30v rated mosfet with 20a current capability is suitable. an exemplary mosfet having these characteristic is fds8812nz from fairchild. from fds8812nz datasheet: ? n-channel mosfet ? v ds = 30v ? i d = 20a continuous drain current ? v gs ( max )= 20v ? r ja = 50c/w ? r ds(on) =3.2m typical at i d =10a, v gs =8v, t j =25c reverse current threshold is: a m mv onrds reversevth reverseis 87.1 2.3 6 )( . . ?= ? = = power dissipation: rds(on) is 4.2m maximum at 25c & 8vgs and will increase as the temperature increases. add 25c to maximum ambient temperature to compensate for the temperature rise due to power dissipation. at 100c (75c + 25c) rds(on) will increase by 28%. =?= m monrds 37.528.12.4)( maximum at 100c )( 2 onrdsisrthtrise ja ??= maximum junction temperature tris e tt a j += max cma w c ct j = ? ? ? ? ? ? ?? += 102 37.5)10( 50 75 2 max 3. vaux: make sure vaux voltage is higher than vin (power source output) by the voltage required to fully enhance the mosfet. in this case there is sufficient headroom on the vaux supply to increase the vgs level fo r a reduction in power dissipation due to lower rds(on). if the mosfet requires 8.0v to achieve lower power dissipation, then vaux = vin + vgs + 0.5v = 12v + 8.0v + 0.5v = 20.5v. when vin is off (0v), pi2001 gnd pin is at 0v and vaux is higher than the vc clamp voltage. a bias resistor (rbias) is needed in series with the vc pin. rbias value: = ? = ? = k ma vv ic vc vaux rbias clamp 45.1 2.4 5.156.21 max min or 1.30k rbias resistor power dissipation rating: note: use minimum value for vc clamp voltage to calculate worst condition power dissipation. mw k vv r bias vc vaux pd clamp rbias 100 30.1 )0.154.26( ) ( 2 2 max = ? = ? = figure 16: pi2001 in floating application: example 2 picor corporation ? picorpower.com pi2001 rev 1.0 page 17 of 23 4. sp and sn pins: since the pi2001 controller gnd pin is connected to t he input (vin) which is also the mosfet source, connect the sp pin directly to the pi2001 gnd pin to reduce the parasitic between the sp pin and the gnd pin to avoid negative voltages on the sp pin with respect to gnd pin. connect the sn pin to the mosfet drain pin. 5. bk pin: connect the bk pin to the gnd pin to achieve the minimum reverse current response time. 6. sl pin: not required, so leave floating. 7. f t pin : the f t pin output is referenced to the pi2001 gnd pin which is connected to vin. a level shift circuit can be added to make the f t pin output referenced to the system ground. the recommended level shift circuit is shown in figure 16, the level shift circuit uses a dual bias resistor transistor circuit which is available as a small device that contains two transistors and their bias resistors, part number nsbc114epdxv6t1. 8. uv and ov inputs: in floating applications these pins can not be used to monitor vin. connect uv to the vc pin and ov to the gnd pin to disable their function. typical application example 3: requirement: redundant bus voltage = -48v (-36v to -60v, 100v for 100ms transient) load current = 5a load (assume through each redundant path) maximum ambient temperature = 60c solution: 1. a single pi2001 with a suitable mosfet for each redundant -48v power source should be used and configured as shown in figure 17. the vc is biased from the return line through a bias resistor. 2. select a suitable n-channel mosfet: select the n-channel mosfet with voltage rating higher than the input voltage, vin, plus any expected transient voltages, with a low rds(on) that is capable of supporting the full load current with margin. for instance, a 100v rated mosfet with 10a current capability is suitable. an exemplary mosfet having these characteristic is si4486ey from vishay siliconix. from si4486ey datasheet: ? n-channel mosfet ? v ds = 100v ? i d = 23a continuous drain current at 125c ? v gs ( max ) = 20v ? r ja = 50c/w ? r ds(on) =20m typical at v gs =10v, t j =25c reverse current threshold is: ma m mv onrds reversevth reverseis 300 20 6 )( . . ?= ? = = power dissipation: rds(on) is 25m maximum at 25c & 10vgs and will increase as the temperature increases. add 40c to maximum ambient temperature to compensate for the temperature rise due to power dissipation. at 100c (60c + 40c) rds(on) w ill increase by 63%. = ? = m monrds 4163.125)( maximum at 100c maximum junction temperature c ma w c ct j = ? ? ? ? ? ? ?? += 11141)0.5( 50 60 2 max recalculate based on calculated junction temperature, 115c. at 115c rds(on) will increase by 72%. = ? = m monrds 4372.125)( maximum at 115c c ma w c ct j = ? ? ? ? ? ? ?? += 113 43)0.5( 50 60 2 max picor corporation ? picorpower.com pi2001 rev 1.0 page 18 of 23 vaux: connect each controller to the return path with a separate bias resistor, rbias. picor corporation ? picorpower.com pi2001 rev 1.0 page 19 of 23 to reduce power dissipation, is selected at 13v which is less than the actual pi2001 clamp voltage (15v typical). 13v is higher than pi2001 maximum gate clamp voltage (10.5v). rbias clamp vc = ? = ? = k ma vv ic vc vaux rbias clamp 48.5 2.4 1336 max min or 5.49k rbias maximum power dissipation is at maximum input voltage and minimum clamp voltage mw k vv r bias vc vaux pd clampmin rbias 369 49.5 )1560( ) ( 2 2 max = ? = ? = 3. sp and sn pins: connect the sp pin to the mosfet source and controller gnd pin, and connect the sn pin to vin- and the drain of the mosfet. 4. bk pin: connect the bk pin to the gnd pin to achieve the minimum reverse current response time. 5. sl pin: not required, so leave floating. 6. f t pin : connect the f t pin to logic input and to the logic power supply or to the vc pin via a resistor. 7. uv and ov inputs: sensing input voltages vin1- and vin2- separately in this application the resistor divider has to be connected between vin1-/vin2- and return. the pi2001 controller gnd pins are referenced to the load side, if the resistor dividers are connected between return and vin1-/vin2- it will produce an error due the voltage drop across the mosfet and will expose the ov and uv controller inputs to a high current in case of an input short circuit and will damage the controller. the voltage across the load can be monitored by one controller or both. the following shows the resistor voltage divider configuration using the three-resistor divider configuration: set a i ra 100 = == = k a mv i uvv ra ra th 5 100 500 )( or 4.99k 1% ? ? ? ? ? ? ? ? ? = 1 )( )( uvv ovv rarb = ? ? ? ? ? ? ?= k v v k 55.41 34 65 99.4 or rb=4.53k () ? ? ? ? ? ? ? ? ? += 1 )( )( th uvv uvv rbrarc () = ? ? ? ? ? ? ? += k mv v kkrc 6381 500 34 53.499.4 or 634k 1% figure 17: pi2001 in low side -48v application layout recommendation: use the following general guidelines when designing printed circuit boards. an example of the typical land pattern for a tdfn pi2001 and so-8/powerpak mosfet is shown in figure 18: ? it is best to connect the gate of the mosfet to the gate pin of the controller with a short and wide trace. ? the gnd pin of the controller carries high peak current and it should be returned to the ground plane through a low impedance path. ? connections from the sp and sn pins to the mosfet source and drain pins respectively should be as short as possible ? the vc bypass capacitor should be located as close as possible to the vc and gnd pins. place the pi2001 and vc bypass capacitor on the same layer of the board. the vc pin and c vc pcb trace should not contain any vias. ? connect all mosfet source pins together with a wide trace to reduce trace parasitics and to accommodate the high current input. similarly, connect all mosfet drain pins together with a wide trace to accommodate the high current output. ? connect the power source very close to the mosfet source connection to reduce the effects of stray parasitics. if a short trace is not possible, connect c4 (typically 1f) as shown in figure 18. figure 18: pi2001 and mosfet layout recommendation picor corporation ? picorpower.com pi2001 rev 1.0 page 20 of 23 package drawing: 10 lead tdfn picor corporation ? picorpower.com pi2001 rev 1.0 page 21 of 23 package drawing: 8 lead soic notes: 0.058 0.003[1.470.08] r0.04 [r0.10] (all) r0.04 [r0.10] (all) see detail "a" 0.194+0.002,-0.005[493+0.005,-0.13] 0.236 0.008[5.990.20] 0.064 0.005[1.630.13] 0.006 0.002[0.150.05] 0.008 +0.0015,-0.0005[0.20+0.038,-0.013] 0.155 +0.002,-0.005[3.94+0.05,-0.13] seating plane base plane 0.050 [1.27] (ref.) (scale: 25:1) top view 7 pin 1# bottom view end view side view detail "a" 0.013 0.003[0.330.08] x 45 0.026 [0.66] 0.016 0.003[0.410.08] 1. all dimensions are shown in inches [mm]. 2. mold flash or protrusions shall not exceed 0.006 [0.15] per side. 3. formed leads shall be planar with repect to one another within 0.003 [0.08] at seating plan. 4. general angle tolerances to be +/-2". 5. general tolerances to be +/- 0.005 [0.13]. 6. this pod complies to ms-012 issue c. ordering information part number package transport media pi2001-00-qeig 3mm x 3mm 10 lead tdfn tape & reel PI2001-00-SOIG 8 lead soic tape & reel picor corporation ? picorpower.com pi2001 rev 1.0 page 22 of 23 picor corporation ? picorpower.com pi2001 rev 1.0 page 23 of 23 warranty vicor products are guaranteed for two years from date of sh ipment against defects in material or workmanship when in normal use and service. this warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. vicor shall not be liable for collateral or consequential damage. this warranty is extended to the original purchaser only. except for the foregoing express warranty, vicor makes no warranty, express or limited, including, but not limited to, the warranty of merchantability or fitness for a particular purpose. vicor will repair or replace defective products in accordance with its own best judgment. for service under this warranty, the buyer must contact vicor to obtain a re turn material authorization (rma) number and shipping instructions. products returned without prior authorization w ill be returned to the buyer. the buyer will pay all charges incurred in returning the produ ct to the factory. vicor w ill pay all reshipment charges if the product was defective within the terms of this warranty. information published by vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. vicor does not assume any liability arisin g out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. per vicor terms and conditions of sale, the user of vicor components in life support applications assumes all risks of such use and indemnifies vicor against all damages. vicor?s comprehensive line of power solu tions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. all sales are subject to vicor?s terms and conditions of sale, which are available upon request. specifications are subject to change without notice. vicor corporation picor corporation 25 frontage road 51 industrial drive andover, ma 01810 north smithfield, ri 02896 usa usa customer service: custserv@vicorpower.com technical support: apps@vicorpower.com tel: 800-735-6200 fax: 978-475-6715 |
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